1. Field of the Invention
The invention relates to a high-voltage power device, and more particularly to a gate layer and a P body used for an LDMOS transistor.
2. Description of the Related Art
Recently, as the manufacturing techniques of semiconductor integrated circuits have developed, to fulfill requests for the integration of controllers, memories, low-voltage operating circuits and high-voltage power devices on a single chip, to achieve a single-chip system, in which a power device, including vertical diffused MOS (VDMOS) transistor, lateral diffused MOS (LDMOS) transistor and insulated gate bipolar transistor (IGBT), is used to increase power transforming efficiency and decrease wasted energy. The LDMOS transistor compatible with the high-voltage CMOS process is prevalent in the manufacture of high-voltage power devices.
FIG. 1 is a sectional diagram of a conventional LDMOS transistor. In a case of a high-voltage area of a P-type semiconductor silicon substrate 10, an N-type epitaxial layer 12 is provided thereon, and a shallow trench isolation (STI) structure 14 is formed in the N-type epitaxial layer 12 to isolate components within the high-voltage area. An N+-type source region 16 is formed in the N-type epitaxial layer 12 and at one side of the STI structure 14. An N+-type drain region 18 is formed in the N-type epitaxial layer 12 and at the other side of the STI structure 14. A P body 20 is formed in the N-type epitaxial layer 12 to surround the sidewalls and bottom of the N+-type source region 16. A gate insulating layer 22 is deposited on the N-type epitaxial layer 12, and a gate layer 24 is patterned on the gate insulating layer 22. The P body 20 has a lateral extension distance LD beneath the gate layer 24 and is defined as an effective channel length of the LDMOS transistor.
FIG. 2 is a plane view of the gate layer 24 and the P body 20 shown in FIG. 1. The periphery of the gate layer 24 overlaps the periphery of the P body 20 to provide effective channel length, and the overlapping width A must be precisely controlled to ensure the electrical performance of the LDMOS transistor. Thus, it is very important to modify the width W of the gate layer 24, the width B of the P body 20 and the overlapping width A to achieve demands for narrowed size and lower process cost. However, the limitations in small-size design and thermal budget always cause the overlapping portion to shift, resulting in the effective channel length LD being to long or too short.
In one approach to the LDMOS transistor, the gate layer 24 is patterned on the gate insulating layer 22 prior to the ion implantation and thermal treatment for forming the P body 20. However, when the width W of the gate layer 24 is narrowed reach 0.35 μm or 0.25 μm, the reduced thermal budget limits the vertical-diffusing distance and the lateral-diffusing distance of the P body 20, thus the overlapping width A cannot achieve the demand for the effective channel length LD.
In another approach to the LDMOS transistor, the processes consisting of ion implantation and thermal treatment for the P body 20 are completed prior to the processes consisting of deposition, photolithography and etching for the gate layer 24. Nevertheless, due to the exposure limitation, the gate layer 24 may shift and fail to precisely control the overlapping width A.